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rev.1.0 _00 125 c operation spi serial e 2 prom for automotive electric component S-25A640A seiko instruments inc. 1 the S-25A640A is a spi serial e 2 prom which operates under the high temperat ure, at high speed, with low current consumption and the wide r ange operation. the S-25A640A respectively has the capacity of 64 kbit and the organization of 8192 words 8-bit, is able to page write and sequential read. ? features ? wide range operation read: 2.5 v to 5.5 v write: 2.5 v to 5.5 v ? operation frequency 5.0 mhz (4.5 v to 5.5 v, at ? 40c to + 125c) ? spi mode (0, 0) and (1, 1) ? page write 32 bytes / page ? sequential read ? monitors write to the memory by a status register ? write protect: software, hardware ? protect area: 25%, 50%, 100% ? write protect function dur ing the low power supply ? function to prevent malfunction by monitoring clock pulse ? cmos schmitt input ( cs , sck, si, wp , hold ) ? endurance: 10 6 cycles/word *1 (at + 85c) 8 10 5 cycles/word *1 (at + 105c) 5 10 5 cycles/word *1 (at + 125c) *1. for each address (word: 8-bit) ? data retention: 100 years (at + 25c), 50 years (at + 125c) ? memory capacitance: 64 kbit ? data before shipment: memory arra y ffh, srwd = 0, bp1 = 0, bp0 = 0 ? lead-free product ? package drawing code package name package tape reel 8-pin sop (jedec) fj008-a fj008-d fj008-d caution before using the product in medical equipment or automobile equipment including car audio, keyless entry and engine control unit, contact to sii is indispensable.
125 c operation spi serial e 2 prom for automotive electric component S-25A640A rev.1.0 _00 seiko instruments inc. 2 ? pin configuration 8-pin sop (jedec) top view table 1 pin no. symbol description 1 cs *1 chip select input 2 so serial data output 3 wp *1 write protect input 4 gnd ground 5 si *1 serial data input 6 sck *1 serial clock input 7 hold *1 hold input 8 vcc power supply *1. all input pins have the cmos struct ure. do not set the input pins in high impedance during operation. so cs 1 2 3 4 8 7 6 5 sck wp gnd si hold vcc figure 1 S-25A640A0a-j8t2ud S-25A640A0h-j8t2ud remark see dimensions for details of the package drawings.
125 c operation spi serial e 2 prom for automotive electric component rev.1.0 _00 S-25A640A seiko instruments inc. 3 ? block diagram mode decoder status register address register data register wp cs hold si sck so vcc gnd memory cell array status memory cell array voltage detector read circuit clock counter y decoder x decoder input control circuit output control circuit step-up circuit page latch figure 2
125 c operation spi serial e 2 prom for automotive electric component S-25A640A rev.1.0 _00 seiko instruments inc. 4 ? absolute maximum ratings table 2 item symbol absolute maximum rating unit power supply voltage v cc ? 0.3 to + 7.0 v input voltage v in ? 0.3 to + 7.0 v output voltage v out ? 0.3 to v cc + 0.3 v operation ambient temperature t opr ? 40 to + 125 c storage temperature t stg ? 65 to + 150 c caution the absolute maximum ratings are rated values exceeding which the product could suffer physical damage. these values must theref ore not be exceeded under any conditions. ? recommended operating conditions table 3 item symbol condition min. max. unit read operation 2.5 5.5 v power supply voltage v cc write operation 2.5 5.5 v high level input voltage v ih v cc = 2.5 v to 5.5 v 0.7 v cc v cc + 1.0 v low level input voltage v il v cc = 2.5 v to 5.5 v ? 0.3 0.3 v cc v ? pin capacitance table 4 (ta = + 25 c, f = 1.0 mhz, v cc = 5 v) item symbol condition min. max. unit input capacitance c in v in = 0 v ( cs , sck, si, wp , hold ) ? 8 pf output capacitance c out v out = 0 v (so) ? 10 pf ? endurance table 5 item symbol operation ambient temperature min. max. unit ? 40c to + 85c 10 6 cycles / word *1 ? 40c to + 105c 8.0 10 5 cycles / word *1 endurance n w ? 40c to + 125c 5.0 10 5 cycles / word *1 *1. for each address (word: 8 bits) ? data retention table 6 item symbol operation ambient temperature min. max. unit + 25c 100 year data retention + 125c 50 year
125 c operation spi serial e 2 prom for automotive electric component rev.1.0 _00 S-25A640A seiko instruments inc. 5 ? dc electrical characteristics table 7 ? 40c to + 125c item symbol condition v cc = 2.5 v to 3.0 v f sck = 2.5 mhz v cc = 3.0 v to 4.5 v f sck = 3.5 mhz v cc = 4.5 v to 5.5 v f sck = 5.0 mhz unit min. max. min. max. min. max. current consumption (read) i cc1 no load at so pin 1.5 2.0 2.5 ma table 8 ? 40c to + 125c item symbol condition v cc = 2.5 v to 3.0 v f sck = 2.5 mhz v cc = 3.0 v to 4.5 v f sck = 3.5 mhz v cc = 4.5 v to 5.5 v f sck = 5.0 mhz unit min. max. min. max. min. max. current consumption (write) i cc2 no load at so pin 4.0 5.0 6.0 ma table 9 ? 40c to + 85c + 85c to + 125c v cc = 2.5 v to 4.5 v v cc = 4.5 v to 5.5 v v cc = 2.5 v to 4.5 v v cc = 4.5 v to 5.5 v item symbol condition min. max. min. max. min. max. min. max. unit standby current consumption i sb cs = vcc, so = open other inputs are v cc or gnd 2.0 3.0 8.0 10.0 a input leakage current i li v in = gnd to v cc 1.0 1.0 2.0 2.0 a output leakage current i lo v out = gnd to v cc 1.0 1.0 2.0 2.0 a v ol1 i ol = 2.0 ma 0.4 0.4 v low level output voltage v ol2 i ol = 1.5 ma 0.4 0.4 0.4 0.4 v v oh1 i oh = ? 2.0 ma 0.8 v cc 0.8 v cc v high level output voltage v oh2 i oh = ? 0.4 ma 0.8 v cc 0.8 v cc 0.8 v cc 0.8 v cc v ? ac electrical characteristics table 10 measurement conditions input pulse voltage 0.2 v cc to 0.8 v cc output reference voltage 0.5 v cc output load 100 pf
125 c operation spi serial e 2 prom for automoti v e electric component S-25A640A rev.1.0 _00 seiko instruments inc. 6 table 11 S-25A640A0h ( ? 40 c to + 105 c) ? 40 c to + 105 c v cc = 2.5 v to 5.5 v v cc = 3.0 v to 5.5 v v cc = 4.5 v to 5.5 v item symbol min. max. min. max. min. max. unit sck clock frequency f sck ? 3.5 ? 5.0 ? 5.0 mhz cs setup time during cs falling t css.cl 90 ? 90 ? 90 ? ns cs setup time during cs rising t css.ch 90 ? 90 ? 90 ? ns cs deselect time t cds 160 ? 140 ? 140 ? ns cs hold time during cs falling t csh.cl 90 ? 90 ? 90 ? ns cs hold time during cs rising t csh.ch 90 ? 90 ? 90 ? ns sck clock time ?h? *1 t high 125 ? 95 ? 95 ? ns sck clock time ?l? *1 t low 125 ? 95 ? 95 ? ns rising time of sck clock *2 t rsk ? 1 ? 1 ? 1 s falling time of sck clock *2 t fsk ? 1 ? 1 ? 1 s si data input setup time t ds 20 ? 20 ? 20 ? ns si data input hold time t dh 30 ? 30 ? 30 ? ns sck ?l? hold time during hold rising t skh.hh 70 ? 70 ? 70 ? ns scl ?l? hold time during hold fa lling t skh.hl 40 ? 40 ? 40 ? ns sck ?l? setup time during hold fa lling t sks.hl 0 ? 0 ? 0 ? ns sck ?l? setup time during hold rising t sks.hh 0 ? 0 ? 0 ? ns disable time of so output *2 t oz ? 100 ? 100 ? 100 ns delay time of so output t od ? 120 ? 90 ? 90 ns hold time of so output t oh 0 ? 0 ? 0 ? ns rising time of so output *2 t ro ? 80 ? 70 ? 70 ns falling time of so output *2 t fo ? 80 ? 70 ? 70 ns disable time of so output during hold falling *2 t oz.hl ? 100 ? 100 ? 100 ns delay time of so output during hold rising *2 t od.hh ? 80 ? 80 ? 80 ns wp setup time t ws1 0 ? 0 ? 0 ? ns wp hold time t wh1 0 ? 0 ? 0 ? ns wp release / setup time t ws2 0 ? 0 ? 0 ? ns wp release / hold time t wh2 150 ? 150 ? 150 ? ns *1. the clock cycle of the sck clock (frequency f sck ) is 1/f sck s. this clock cycle is determined by a combination of several ac characteristics. note that the clock cycle cannot be set as (1/f sck ) = t low (min.) + t high (min.) by minimizing the sck clock cycle time. *2. these are values of sample and not 100% tested.
125 c operation spi serial e 2 prom for automotive electric component rev.1.0 _00 S-25A640A seiko instruments inc. 7 table 12 S-25A640A0a ( ? 40 c to + 125 c) ? 40 c to + 125 c v cc = 2.5 v to 5.5 v v cc = 3.0 v to 5.5 v v cc = 4.5 v to 5.5 v item symbol min. max. min. max. min. max. unit sck clock frequency f sck ? 2.5 ? 3.5 ? 5.0 mhz cs setup time during cs falling t css.cl 120 ? 90 ? 90 ? ns cs setup time during cs rising t css.ch 120 ? 90 ? 90 ? ns cs deselect time t cds 210 ? 160 ? 140 ? ns cs hold time during cs falling t csh.cl 120 ? 90 ? 90 ? ns cs hold time during cs rising t csh.ch 120 ? 90 ? 90 ? ns sck clock time ?h? *1 t high 160 ? 125 ? 95 ? ns sck clock time ?l? *1 t low 160 ? 125 ? 95 ? ns rising time of sck clock *2 t rsk ? 1 ? 1 ? 1 s falling time of sck clock *2 t fsk ? 1 ? 1 ? 1 s si data input setup time t ds 30 ? 20 ? 20 ? ns si data input hold time t dh 40 ? 30 ? 30 ? ns sck ?l? hold time during hold rising t skh.hh 90 ? 70 ? 70 ? ns scl ?l? hold time during hold fa lling t skh.hl 50 ? 40 ? 40 ? ns sck ?l? setup time during hold fa lling t sks.hl 0 ? 0 ? 0 ? ns sck ?l? setup time during hold rising t sks.hh 0 ? 0 ? 0 ? ns disable time of so output *2 t oz ? 130 ? 100 ? 100 ns delay time of so output t od ? 160 ? 120 ? 90 ns hold time of so output t oh 0 ? 0 ? 0 ? ns rising time of so output *2 t ro ? 110 ? 80 ? 80 ns falling time of so output *2 t fo ? 110 ? 80 ? 80 ns disable time of so output during hold fa lling *2 t oz.hl ? 130 ? 100 ? 100 ns delay time of so output during hold rising *2 t od.hh ? 110 ? 80 ? 80 ns wp setup time t ws1 0 ? 0 ? 0 ? ns wp hold time t wh1 0 ? 0 ? 0 ? ns wp release / setup time t ws2 0 ? 0 ? 0 ? ns wp release / hold time t wh2 200 ? 150 ? 150 ? ns * 1. the clock cycle of the sck clock (frequency f sck ) is 1/f sck s. this clock cycle is determined by a combination of several ac characteristics. note that the clock cycle cannot be set as (1/f sck ) = t low (min.) + t high (min.) by minimizing the sck clock cycle time. * 2. these are values of sample and not 100% tested.
125 c operation spi serial e 2 prom for automoti v e electric component S-25A640A rev.1.0 _00 seiko instruments inc. 8 table 13 S-25A640A0h, S-25A640A0a ( ? 40 c to + 85 c) ? 40c to + 85c v cc = 2.5 v to 5.5 v v cc = 3.0 v to 5.5 v v cc = 4.5 v to 5.5 v item symbol min. max. min. max. min. max. unit sck clock frequency f sck ? 3.5 ? 5.0 ? 5.0 mhz cs setup time during cs falling t css.cl 90 ? 90 ? 90 ? ns cs setup time during cs rising t css.ch 90 ? 90 ? 90 ? ns cs deselect time t cds 160 ? 140 ? 140 ? ns cs hold time during cs falling t csh.cl 90 ? 90 ? 90 ? ns cs hold time during cs rising t csh.ch 90 ? 90 ? 90 ? ns sck clock time ?h? *1 t high 125 ? 95 ? 95 ? ns sck clock time ?l? *1 t low 125 ? 95 ? 95 ? ns rising time of sck clock *2 t rsk ? 1 ? 1 ? 1 s falling time of sck clock *2 t fsk ? 1 ? 1 ? 1 s si data input setup time t ds 20 ? 20 ? 20 ? ns si data input hold time t dh 30 ? 30 ? 30 ? ns sck ?l? hold time during hold rising t skh.hh 70 ? 70 ? 70 ? ns scl ?l? hold time during hold fa lling t skh.hl 40 ? 40 ? 40 ? ns sck ?l? setup time during hold fa lling t sks.hl 0 ? 0 ? 0 ? ns sck ?l? setup time during hold rising t sks.hh 0 ? 0 ? 0 ? ns disable time of so output *2 t oz ? 100 ? 100 ? 100 ns delay time of so output t od ? 120 ? 90 ? 90 ns hold time of so output t oh 0 ? 0 ? 0 ? ns rising time of so output *2 t ro ? 80 ? 70 ? 70 ns falling time of so output *2 t fo ? 80 ? 70 ? 70 ns disable time of so output during hold fa lling *2 t oz.hl ? 100 ? 100 ? 100 ns delay time of so output during hold rising *2 t od.hh ? 80 ? 80 ? 80 ns wp setup time t ws1 0 ? 0 ? 0 ? ns wp hold time t wh1 0 ? 0 ? 0 ? ns wp release / setup time t ws2 0 ? 0 ? 0 ? ns wp release / hold time t wh2 150 ? 150 ? 150 ? ns *1. the clock cycle of the sck clock (frequency f sck ) is 1/f sck s. this clock cycle is determined by a combination of several ac characteristics. note that the clock cycle cannot be set as (1/f sck ) = t low (min.) + t high (min.) by minimizing the sck clock cycle time. *2. these are values of sample and not 100% tested.
125 c operation spi serial e 2 prom for automotive electric component rev.1.0 _00 S-25A640A seiko instruments inc. 9 table 14 ? 40c to + 125c v cc = 2.5 v to 5.5 v item symbol min. max. unit write time t pr ? 4.0 ms so t csh.cl sck cs si t css.cl t ds t dh msb in lsb in t csh.ch t css.ch t cds t fsk t rsk high-z figure 3 serial input timing so sck hold cs si t skh.hl t oz.hl t od.hh t skh.hh t sks.hl t sks.hh figure 4 hold timing
125 c operation spi serial e 2 prom for automotive electric component S-25A640A rev.1.0 _00 seiko instruments inc. 10 so sck cs si t high t oh t ro t oz t low t sck t od t fo t od t oh addr lsb in lsb out figure 5 serial output timing wp cs t wh1 t ws1 figure 6 valid timing in write protect wp cs t wh2 t ws2 figure 7 invalid timing in write protect
125 c operation spi serial e 2 prom for automotive electric component rev.1.0 _00 S-25A640A seiko instruments inc. 11 ? pin function 1. cs (chip select input) pin this is an input pin to set a chip in the select status. in t he ?h? input level, the device is in the non-select status and its output is high impedance. the devic e is in standby as long as it is not in write inside. the device goes in active by setting the chip select to ?l?. input any instruction code after pow er-on and a falling of chip select. 2. si (serial data input) pin this pin is to input serial data. this pin receives an in struction code, an address and writ e data. this pin latches data at rising edge of serial clock. 3. so (serial data output) pin this pin is to output serial data. the data output changes at falling edge of serial clock. 4. sck (serial clock input) pin this is a clock input pin to set the timing of serial data. an instruction code, an addre ss and write data are received at a rising edge of clock. data is output at falling edge of clock. 5. wp (write protect input) pin write protect is purposed to pr otect the area size against the write instruction (bp1, bp0 in the status register). fix this pin ?h? or ?l? not to se t it in the floating state. refer to ? ? protect operation ? for details. 6. hold (hold input) pin this pin is used to pause serial communications wi thout setting the device in the non-select status. in the hold status, the serial output goes in high impedance, t he serial input and the serial clock go in ?don?t care?. during the hold operation, be sure to set the dev ice in active by setting the chip select ( cs pin) to ?l?. refer to ? ? hold operation ? for details.
125 c operation spi serial e 2 prom for automotive electric component S-25A640A rev.1.0 _00 seiko instruments inc. 12 ? instruction setting table 15 is the list of instruction for the S-25A640A. t he instruction is able to be input by changing the cs pin ?h? to ?l?. input the instruction in the msb first. each instruction code is or ganized with 1-byte as shown below. if the s- 25a640a receives any invalid instruction code, the device goes in t he non-select status. table 15 instruction code address data instruction operation sck input clock 1 to 8 sck input clock 9 to 16 sck input clock 17 to 24 sck input clock 25 to 32 wren write enable 0000 0110 ? ? ? wrdi write disable 0000 0100 ? ? ? rdsr read the status register 0000 0101 b7 to b0 output *1 ? ? wrsr write in the status register 0000 0001 b7 to b0 input ? ? read read memory data 0000 0011 a15 to a8 *2 a7 to a0 d7 to d0 output *3 write write memory data 0000 0010 a15 to a8 *2 a7 to a0 d7 to d0 input *1. sequential data reading is possible. *2. the higher addresses a15 to a13 = don?t care. *3. after outputting data in the specified addr ess, data in the following address is output.
125 c operation spi serial e 2 prom for automotive electric component rev.1.0 _00 S-25A640A seiko instruments inc. 13 ? operation 1. status register the status register?s organization is below. the status register can write and read by a specific instruction. srwd 0 b7 b6 0 b5 0 b4 bp1 b3 bp0 b2 wel b1 wip b0 status register write disable block protect bits write enable latch write in progress figure 8 organization of status register the status/control bits of the st atus register are as follows. 1. 1 srwd (b7) : status register write disable bit srwd operates in conjunction with the write protect signal ( wp ). with a combination of bit srwd and signal wp (srwd = ?1?, wp = ?l?), this device goes in hardware protect st atus. in this case, the bits composed of the nonvolatile bit in the status register (srwd, bp1, bp0) go in read only, so that the wrsr in struction is not be performed. 1. 2 bp1, bp0 (b3, b2) : block protect bit bp1 and bp0 are composed of the nonvolatile bit. the ar ea size of software protect against write instruction is defined by them. rewriting these bits is possible by the wrsr instructi on. to protect the memory area against the write instruction, set either or both of bit bp1 and bp0 to ?1?. rewriting bit bp1 and bp0 is possible unless they are in hardware protect mode. refer to ? ? protect operation ? for details of ?block protect?. 1. 3 wel (b1) : write enable latch bit wel shows the status of internal write enable latch. bit wel is set by the wren instruction only. if bit wel is ?1?, this is the status that write enable latch is set. if bit wel is ?0?, write enable latch is in reset, so that the s- 25a640a does not receive the write or wrsr instru ction. bit wel is reset after these operations; ? the power supply voltage is dropping ? power-on ? after performing wrdi ? after the write operation by the wrsr instruction ? after the write operation by the write instruction
125 c operation spi serial e 2 prom for automotive electric component S-25A640A rev.1.0 _00 seiko instruments inc. 14 1. 4 wip (b0) : write in progress bit wip is read only and shows whether the internal memo ry is in the write operati on or not by the write or wrsr instruction. bit wip is ?1? during the write operation but ?0? dur ing any other status. figure 9 shows the usage example. d2 d1 d0 rdsr rdsr rdsr cs si 000 11 000 11 000 00 wel, wip wel, wip wel, wip so write or wrsr instruction rdsr instruction rdsr instruction rdsr instruction t pr s r w d b p 1 b p 0 s r w d b p 1 b p 0 s r w d b p 1 b p 0 figure 9 usage example of wel, wip bits during write
125 c operation spi serial e 2 prom for automotive electric component rev.1.0 _00 S-25A640A seiko instruments inc. 15 2. write enable (wren) before writing data (write and wrsr), be sure to set bit writ e enable latch (wel). this instruction is to set bit wel. its operation is below. after selecting the device by the chip select ( cs ), input the instruction code from se rial data input (si). to set bit wel, set the device in the non-select status by cs at the 8th clock of the serial clock (sck). to cancel the wren instruction, input the clock different from a specified value (n = 8 clock) while cs is in ?l?. so sck wp cs si instruction high-z 12345678 high / low figure 10 wren operation
125 c operation spi serial e 2 prom for automotive electric component S-25A640A rev.1.0 _00 seiko instruments inc. 16 3. write disable (wrdi) the wrdi instruction is one of ways to reset bit write enable latch (wel). after selecting t he device by the chip select ( cs ), input the instruction code from serial data input (si). to reset bit wel, set the devic e in the non-select status by cs at the 8th clock of the seri al clock. to cancel the wrdi instruction, input the clock different from a specified value (n = 8 clock) while cs is in ?l?. bit wel is reset after the operations shown below. ? the power supply voltage is dropping ? power-on ? after performing wrdi ? after the completion of write operation by the wrsr instruction ? after the completion of write operation by the write instruction so sck wp cs si instruction high-z 12345678 high / low figure 11 wrdi operation
125 c operation spi serial e 2 prom for automotive electric component rev.1.0 _00 S-25A640A seiko instruments inc. 17 4. read the status register (rdsr) reading data in the status regi ster is possible by the rdsr instruction. during the write operation, it is possible to confirm the progress by checking bit wip. set the chip select ( cs ) ?l? first. after that, input the instruction code from serial data input (si). t he status of bit in the status register is output from serial data output (so). sequent ial read is available for the status register. to stop the read cycle, set cs to ?h?. it is possible to read the status register always. the bits in it are valid and can be read by rdsr even in the write cycle. however, during the write cycle in progr ess, the nonvolatile bits srwd, bp1, bp0 are fixed in a certain value. these updated values of bit can be obtained by inputting another new rdsr instruction a fter the write cycle has completed. contrarily, two of read only bits wel and wip are being updated while the write cycle is in progress. so sck wp cs si instruction high-z 12345678 high / low 9 10111213141516 outputs data in the status register b7 b6 b5 b7 b0 b1 b2 b3 b4 figure 12 rdsr operation
125 c operation spi serial e 2 prom for automotive electric component S-25A640A rev.1.0 _00 seiko instruments inc. 18 5. write in the status register (wrsr) the values of status register (srwd, bp1, bp0) can be rewritten by inputting the wrsr instruction. but b6, b5, b4, b1, b0 of status register cannot be re written. b6 to b4 are always ?0? when reading the status register. before inputting the wrsr instruction, set bit wel by the wren instruction. the operati on of wrsr is shown below. set the chip select ( cs ) ?l? first. after that, input the instruction c ode and data from serial data input (si). to start wrsr write (t pr ), set the chip select ( cs ) to ?h? after inputting data or before i nputting a rising of the next serial clock. it is possible to confirm the operation st atus by reading the value of bit wip dur ing wrsr write. bit wip is ?1? during write, ?0? during any other status. bit wel is reset when write is completed. with the wrsr instruction, the val ues of bp1 and bp0; which determine the area size the users can handle as the read only memory; can be changed. besides bit srwd c an be set or reset by the wrsr instruction depending on the status of write protect wp . with a combination of bit srwd and write protect wp , the device can be set in hardware protect mode (hpm). in this case, the wrsr instruction is not be performed (refer to ? ? protect operation ?). bit srwd and bp1, bp0 keep the value which is the one prior to the wrsr instruction dur ing the wrsr instruction. the newly updated value is changed when the wrsr instruction has completed. to cancel the wrsr instruction, input the clock different from a s pecified value (n = 16 clock) while cs is in ?l?. so sck wp cs si instruction high-z 12345678 high / low 9 10111213141516 inputs data in the status register b7 b6 b5 b0 b1 b2 b3 b4 figure 13 wrsr operation
125 c operation spi serial e 2 prom for automotive electric component rev.1.0 _00 S-25A640A seiko instruments inc. 19 6. read memory data (read) the read operation is shown below. input the instruction code and the address fr om serial data input (si) after inputting ?l? to the chip select ( cs ). the input address is loaded to the internal address counter, and data in the address is output from the serial data output (so). next, by inputting the serial clo ck (sck) keeping the chip select ( cs ) in ?l?, the address is automatically incremented so that data in the following address is sequentially output. the address counter rolls over to the first address by increment in the last address. to finish the read cycle, set cs to ?h?. it is possible to raise the chip se lect always during the cy cle. during write, the read instruction code is not be accepted or operated. so sck wp cs si instruction high-z 12345678 high / low 9 1011 1314151617 16-bit address a15 a14 a13 a0 a1 a2 a3 outputs the first byte d4 d5 d6 d7 18 19 20 21 22 23 24 d0 d1 d2 d3 d7 outputs the second 12 remark the higher addresses a15 to a13 = don?t care. figure 14 read operation
125 c operation spi serial e 2 prom for automotive electric component S-25A640A rev.1.0 _00 seiko instruments inc. 20 7. write memory data (write) figure 15 shows the timing chart when inputting 1-byte data. input the instruction code, the address and data from serial data input (si) after inpu tting ?l? to the chip select ( cs ). to start write (t pr ), set the chip select ( cs ) to ?h? after inputting data or before inputting a rising of the next serial clock. bit wip and wel are reset to ?0? when write has completed. the S-25A640A can page write of 32 bytes. its function to transmit data is as sa me as byte write basically, but it operates page write by receiving sequent ial 8-bit write data as much data as page size has. input the instruction code, the address and data from serial dat a input (si) after inputting ?l? in cs , as the write operat ion (page) shown in figure 16 . input the next data while keeping cs in ?l?. after that, repeat inpu tting data of 8-bit sequentially. at the end, by setting cs to ?h?, the write operation starts (t pr ). 5 of the lower bits in the address are automatically incremented ev ery time when receiving write data of 8-bit. thus, even if write data exceeds 32 bytes, t he higher bits in the address do not change. and 5 of lower bits in the address roll over so that write data which is previously input is overwritten. these are cases when the write instru ction is not acc epted or operated. ? bit wel is not set to ?1? (not set to ?1? beforehand immediately before the write instruction) ? during write ? the address to be written is in the protect area by bp1 and bp0. to cancel the write instructi on, input the clock different fr om a specified value (n = 24+m 8 clock) while cs is in ?l?. so sck wp cs si instruction high-z 12345678 high / low 91011 2122232425 16-bit address a15 a14 a13 a0 a1 a2 a3 data byte 1 d4 d5 d6 d7 26 27 28 29 30 31 32 d0 d1 d2 d3 remark the higher addresses a15 to a13 = don?t care. figure 15 write operation (1 byte)
125 c operation spi serial e 2 prom for automotive electric component rev.1.0 _00 S-25A640A seiko instruments inc. 21 so sck wp cs si instruction high-z 12345678 high / low 9 1011 22232425 16-bit address (n) a15 a14 a13 a0 a1 a2 data byte (n) data byte (n + x) d4 d5 d6 d7 26 27 28 29 30 31 32 d0 d1 d2 d3 d0 d1 d2 d3 d4 remark the higher addresses a15 to a13 = don?t care. figure 16 write operation (page)
125 c operation spi serial e 2 prom for automotive electric component S-25A640A rev.1.0 _00 seiko instruments inc. 22 ? protect operation table 16 shows the block settings of write protect. table 17 shows the protect operation fo r the device. as long as bit srwd, the status register write disable bit, in the status register is reset to ?0? (it is in reset before the shipment), the value of status regi ster can be changed. these are two statuses when bit srwd is set to ?1?. ? write in the status register is possible; write protect ( wp ) is in ?h?. ? write in the status register is impossible; write protect ( wp ) is in ?l?. therefore the writ e protect area which is set by protect bit (bp1, bp0) in the st atus register cannot be changed. these operations are to set hardware protect (hpm). ? after setting bit srwd, set write protect ( wp ) to ?l?. ? set bit srwd completed setting write protect ( wp ) to ?l?. figure 6 and 7 show the valid timing in write protect and invalid ti ming in write protect duri ng the cycle write to the status register. by inputting ?h? to write protect ( wp ), hardware protect (hpm) is released. if the write protect ( wp ) is ?h?, hardware protect (hpm) does not function, software pr otect (spm) which is set by the protec t bits in the status register (bp1, bp0) only works. table 16 the block settings of write protect status register bp1 bp0 the area of write protect addr ess of write protect block 0 0 0 % none 0 1 25 % 1800h to 1fffh 1 0 50 % 1000h to 1fffh 1 1 100 % 0000h to 1fffh table 17 protect operation mode wp pin bit srwd bit wel write protect bl ock general block status register 1 x 0 write disable writ e disable write disable 1 x 1 write disable write enable write enable x 0 0 write disable writ e disable write disable software protect (spm) x 0 1 write disable write enable write enable 0 1 0 write disable write disable write disable hardware protect (hpm) 0 1 1 write disable write enable write disable remark x = don?t care
125 c operation spi serial e 2 prom for automotive electric component rev.1.0 _00 S-25A640A seiko instruments inc. 23 ? hold operation the hold operation is used to pause serial communications wi thout setting the device in t he non-select status. in the hold status, the serial data output goes in high impedance, and both of the serial data input and the serial clock go in ?don?t care?. be sure to set the chip select ( cs ) to ?l? to set the device in the se lect status during the hold status. generally, during the hold status, the device holds the select st atus. but if setting the device in the non-select status, the users can finish the operat ion even in progress. figure 17 shows the hold operation. set hold ( hold ) to ?l? when the serial clock (sck) is in ?l?, hold ( hold ) is switched at the same time the hol d status starts. if setting hold ( hold ) to ?h?, hold ( hold ) is switched at the same time the hold status ends. set hold ( hold ) to ?l? when the serial clock (sck) is in ?h?; t he hold status starts when t he serial clock goes in ?l? after hold ( hold ) is switched. if setting hold ( hold ) to ?h?, the hold status ends when the serial clock goes in ?l? after hold ( hold ) is switched. sck hold hold status hold status figure 17 hold operation
125 c operation spi serial e 2 prom for automotive electric component S-25A640A rev.1.0 _00 seiko instruments inc. 24 ? write protect function during the low power supply voltage the S-25A640A has a built-in detection circuit which operates with the lo w power supply voltage. the S-25A640A cancels the write operation (write, wr sr) when the power supply voltage drops and power-on, at the same time, goes in the write protect st atus (wrdi) automatically to reset bit we l. the detection voltage is 1.20 v typ., the release voltage is 1.35 v typ., and its hy steresis is approx. 0.15 v (refer to figure 18 ). to operate write, after the power suppl y voltage dropped once but rose to the vo ltage level which allows write again, be sure to set the write enable latch bit (w el) before operating write (write, wrsr). in the write operation, data in the address written during the low power supply voltage is not assured . cancel the write instruction set in write protect (wrdi) automatically release voltage ( + ? figure 18 operation during low power supply voltage ? i/o pin 1. connection of input pin all input pins in S-25A640A have the cm os structure. do not set these pi ns in high impedance during operation when you design. especially, set the cs input in the non-select status ?h? dur ing power-on/off and standby. the error write does not occur as long as the cs pin is in the non-sele ct status ?h?. set the cs pin to v cc via a resistor (the pull-up resistor of 10 k ? to 100 k ? ). to prevent the error for sure, it is recommended to set other input pins than the cs pin via a pull-up resistor. 2. equivalent circuit of i/o pin figure 19 and 20 show the equivalent circuits of input pins in S-25A640A. a pu ll-up and pull-down elements are not included in each input pin, pay attention not to set it in the floating state when you design. figure 21 shows the equivalent circuit of the output pin. this pin has the tri-state out put of ?h? level/?l? level/high impedance.
125 c operation spi serial e 2 prom for automotive electric component rev.1.0 _00 S-25A640A seiko instruments inc. 25 2. 1 input pin cs, sck figure 19 cs , sck pin si, wp, hold figure 20 si, wp , hold pin 2. 2 output pin so v cc figure 21 so pin 3. precaution for use absolute maximum ratings: do not operate these ics in excess of the absolute maximu m ratings (as listed on the data sheet). exceeding the supply voltage rating can cause latch-up. operations with moisture on the e 2 prom pins may occur malfunction by short-circuit between pins. especially, in occasions like picking the e 2 prom up from low temperature t ank during the evaluation. be sure that not remain frost on the e 2 prom pin to prevent malfunction by short-circuit. also attention should be paid in using on environmen t, which is easy to dew for the same reason.
125 c operation spi serial e 2 prom for automotive electric component S-25A640A rev.1.0 _00 seiko instruments inc. 26 ? precautions do not apply an electrostatic discharge to this ic that ex ceeds the performance ratings of the built-in electrostatic protection circuit. sii claims no responsibility for any and all disputes arisi ng out of or in connection wi th any infringement of the products including this ic upon patents owned by a third party.
125 c operation spi serial e 2 prom for automotive electric component rev.1.0 _00 S-25A640A seiko instruments inc. 27 ? product name structure S-25A640A 0 x ? j8t2 u d product name S-25A640A: 64 kbit package name (abbreviation) and ic packing specification j8t2: 8-pin sop (jedec), tape burn-in type d: wafer burn-in fixed operating temperature h: 40 c to 105 c a: 40 c to 125 c

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the information described herein is subject to change without notice. seiko instruments inc. is not responsible for any problems caused by circuits or diagrams described herein whose related industrial properties, patents, or other rights belong to third parties. the application circuit examples explain typical applications of the products, and do not guarantee the success of any specific mass-production design. when the products described herein are regulated products subject to the wassenaar arrangement or other agreements, they may not be exported without authorization from the appropriate governmental authority. use of the information described herein for other purposes and/or reproduction or copying without the express permission of seiko instruments inc. is strictly prohibited. the products described herein cannot be used as part of any device or equipment affecting the human body, such as exercise equipment, medical equipment, security systems, gas equipment, or any apparatus installed in airplanes and other vehicles, without prior written permission of seiko instruments inc. although seiko instruments inc. exerts the greatest possible effort to ensure high quality and reliability, the failure or malfunction of semiconductor products may occur. the user of these products should therefore give thorough consideration to safety design, including redundancy, fire-prevention measures, and malfunction prevention, to prevent any accidents, fires, or community damage that may ensue.

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